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Register / Log In 中文 / 한국어 / 日本 / English Powered by Google Übersetzer Menu * Home * Wiki * Forum * EDA Expand child menu * Agnisys * Altair * AMIQ EDA * Ansys, Inc. * Breker Verification Systems * Cadence * Cliosoft * Corigine * Defacto Technologies * Easy-Logic * Empyrean * Infinisim * IROC Technologies * Keysight EDA * Perforce * MunEDA * MZ Technologies * Scientific Analog * Siemens EDA * Synopsys * S2C EDA * yieldHUB * IP Expand child menu * Agile Analog * Alphacore * Alphawave Semi * Analog Bits * Andes Technology * Arteris * Blue Cheetah Analog Design * Certus Semiconductor * Ceva * Codasip * Comcores * Expedera * Mirabilis Design * Mixel * Movellus * Quadric * Semidynamics * sureCore * Synopsys * Truechip * Weebit Nano * Services Expand child menu * Accellera * Alchip * Axiomise * EMD Electronics * TechInsights * Mettler-Toledo * IC Mask Design * IPnest * Planorama Design * Pragmatic * Samtec * Semiconductor Advisors * Semiconductor Intelligence * Silicon Catalyst * Sondrel * TechInsights * TenXerLabs * Foundries Expand child menu * GlobalFoundries * Intel Foundry * Samsung Foundry * Soitec * TSMC * eFPGA / FPGA Expand child menu * Achronix * Flex Logix * Analytics Expand child menu * proteanTecs * Security Expand child menu * Intrinsic ID * PQShield * Secure-IC * Zentera * Books * Job Board * Podcast * LATEST NEWS: * CEO Interviews * EDA * IP * Chiplet * TSMC * Intel * RISC-V * Arm * AI * IoT * Automotive * 5G * Security * Lithography * Events Register / Log In Guests have limited access. Join our community today! You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today! SEARCH SEMIWIKI Blogs JobsWikis Forum All Search RECENT ANSYS, INC. ARTICLES * WHY DID SYNOPSYS REALLY ACQUIRE ANSYS? January 25, 2024 * WILL THE PACKAGE KILL MY HIGH-FREQUENCY CHIP DESIGN? January 2, 2024 * KEYNOTE SPEAKERS ANNOUNCED FOR IDEAS 2023 DIGITAL FORUM October 26, 2023 * ANSYS REVVING UP FOR AUTOMOTIVE AND 3D-IC MULTIPHYSICS SIGNOFF AT DAC 2023 June 26, 2023 * KEYNOTE SNEAK PEEK: ANSYS CEO AJEI GOPAL AT SAMSUNG SAFE FORUM 2023 June 19, 2023 * WEBINAR: REVOLUTIONIZING CHIP DESIGN WITH 2.5D/3D-IC DESIGN TECHNOLOGY June 12, 2023 * CHIPLET Q&A WITH JOHN LEE OF ANSYS May 19, 2023 * ANSYS ACQUIRES ANOTHER! May 16, 2023 * SEMI ESD ALLIANCE CEO OUTLOOK SPONSORED BY KEYSIGHT PROMISES INDUSTRY PERSPECTIVES, INSIGHTS May 11, 2023 * MULTIPHYSICS ANALYSIS FROM CHIP TO SYSTEM April 10, 2023 * CHECKLIST TO ENSURE SILICON INTERPOSERS DON’T KILL YOUR DESIGN March 20, 2023 * HFSS LEADS THE WAY WITH EXPONENTIAL INNOVATION February 28, 2023 * DESIGNCON 2023 PANEL PHOTONICS FUTURE: THE VISION, THE CHALLENGE, AND THE PATH TO INFINITY & BEYOND! February 28, 2023 * EXPONENTIAL INNOVATION: HFSS February 21, 2023 * IDEAS ONLINE TECHNICAL CONFERENCE FEATURES INTEL, QUALCOMM, NVIDIA, IBM, SAMSUNG, AND MORE DISCUSSING CHIP DESIGN EXPERIENCES November 29, 2022 * WHATEVER HAPPENED TO THE BIG 5G AIRPORT CONTROVERSY? PLUS A LOOK TO THE FUTURE September 28, 2022 * ANSYS’ EMERGENCE AS A TIER 1 EDA PLAYER— AND WHAT THAT MEANS FOR 3D-IC September 20, 2022 * WEBINAR: DESIGN AND VERIFY STATE-OF-THE-ART RFICS USING SYNOPSYS / ANSYS CUSTOM DESIGN FLOW August 11, 2022 * WHAT QUANTUM MEANS FOR ELECTRONIC DESIGN AUTOMATION July 6, 2022 * THE LINES ARE BLURRING BETWEEN SYSTEM AND SILICON. YOU’RE NOT READY. July 1, 2022 WP_Term Object ( [term_id] => 34 [name] => Ansys, Inc. [slug] => ansys-inc [term_group] => 0 [term_taxonomy_id] => 34 [taxonomy] => category [description] => [parent] => 157 [count] => 253 [filter] => raw [cat_ID] => 34 [category_count] => 253 [category_description] => [cat_name] => Ansys, Inc. [category_nicename] => ansys-inc [category_parent] => 157 ) WP_Term Object ( [term_id] => 34 [name] => Ansys, Inc. [slug] => ansys-inc [term_group] => 0 [term_taxonomy_id] => 34 [taxonomy] => category [description] => [parent] => 157 [count] => 253 [filter] => raw [cat_ID] => 34 [category_count] => 253 [category_description] => [cat_name] => Ansys, Inc. [category_nicename] => ansys-inc [category_parent] => 157 ) Ansys, Inc. Posted on March 20, 2023February 6, 2024 by Dr. Lang Lin CHECKLIST TO ENSURE SILICON INTERPOSERS DON’T KILL YOUR DESIGN Checklist to Ensure Silicon Interposers Don’t Kill Your Design by Dr. Lang Lin on 03-20-2023 at 10:00 am View Profile View Forum Posts View Articles Private Message Categories: Ansys, Inc., Chiplet, EDA Traditional methods of chip design and packaging are running out of steam to fulfill growing demands for lower power, faster data rates, and higher integration density. Designers across many industries – like 5G, AI/ML, autonomous vehicles, and high-performance computing – are striving to adopt 3D semiconductor technologies that promise to be the solution. The tremendous growth in 2.5 and 3D IC packaging technology has been driven by high-profile early adopters delivering high bandwidth and latency products. CPU and Computer chip concept BENEFITS OF 2.5 AND 3D TECHNOLOGY This trending technology meets the demands of enclosing all functionality in one sophisticated IC package, enabling engineers to meet aggressive high-speed and miniaturization goals. In 3D-IC packaging, dies are stacked vertically on top of each other (e.g. HBM), while 2.5D packaging places bare die (chiplets) next to each other. The chiplets are connected through a silicon interposer and through-chip vias (TSVs). This makes for a much smaller footprint and eliminates bulky interconnects and packaging which can significantly impede data rate and latency performance. Heterogenous integration is another benefit of silicon interposers, enabling engineers to place memory and logic with different silicon technologies in the same package, reducing unnecessary delays and power consumption. Integrating different chips designed in their most appropriate technology nodes provides better performance, cost, and improved time to market when compared to monolithic SOC designs on advanced technology nodes. Monolithic SOCs take longer to design and validate, contributing to increased cost and time to market. The implementation of silicon interposers allows for more configurable system architectures but also poses additional multiphysics challenges like thermal expansion and electromagnetic interference along with fewer design and production issues. CHALLENGES OF 2.5 AND 3D DESIGN Silicon interposers is a successful and booming advancement in IC packaging technology. This technology will soon replace the traditional methods of chip design. Combining different functional blocks and memory within the same package provides high speed and improved performance for advanced design technologies. But the new considerations with interposers impose unfamiliar challenges and designers must understand the power integrity, thermal integrity and signal integrity interactions between the chiplet dies, the interposer, and the package. System simulation becomes an integral factor for the expected performance of the IC package. Interposers act as a passive layer with a coefficient of thermal expansion that matches that of the chiplets, which explains the popularity of silicon for interposers. Nevertheless, it doesn’t eliminate the possibility of thermal hot spots and joule heating problems within the design. Interposers are supported by placing them on an ordinary substrate with a different thermal expansion coefficient, which contributes to increased mechanical stress and interposer warpage. That’s where the designer should be worried about the reliability of the system as this stress can easily crack some of the thousands of microbump connections. Silicon interposers provide significantly denser I/O connectivity allowing higher bandwidth and better use of die space. But as we know, nothing comes for free. Multiple IPs in the same package require multiple power sources, constituting a complex power distribution network (PDN) within the package itself. The PDN runs throughout the entire package and is always vulnerable to power noise leading to power integrity problems. Analyzing the voltage distribution and current signature of every chip in the IC system with an interposer is important for ensuring power integrity. Routing considerable amounts of power through the vertical connections between elements creates more problems for power integrity. These include TSVs and C4 bumps, as well as tiny micro-bumps, and hybrid bonding connections. Last but not least, many high-speed signals are routed among the chips and interposer which can easily fall victim to electromagnetic coupling and crosstalk. Electromagnetic signal integrity, also for high-speed digital signals, must be on your verification list when designing an IC package with interposer. This technology is a cost-effective, high-density, and power-efficient technique but is still susceptible to EM interference, thermal, signal and power integrity issues. Figure2: Block diagram of Multiphysics analysis of multi-die system Power Integrity: Power is the most critical aspect of any IC package design. Everything around the package design is driven by the power consumed by chips within the IC package. Every chip has a different power requirement which leads to requirements for the power delivery network. The PDN also has a critical role in maintaining the power integrity of the IC package by minimizing voltage drop (IR-drop) and avoiding electromigration failures. The best way to achieve power integrity is to optimize the power delivery network by simulating the fluctuating current at each IC and the parasitic of passive elements that make up the PDN. It becomes more complicated with an interposer since chips are connected through the interposer. Power and ground trails routed through the interposer impose new challenges when analyzing power integrity. But it is not the only issue. Electromigration issues come hand in hand with PI problems. The current density in each piece of geometry must be modeled and should be below the maximum limit supplied by the foundry. Joule heating of the microbumps and wires has a significant impact on the maximum allowable current density, which implies a degree of thermal simulation for maximum accuracy. Ansys Redhawk-SC and Totem, can extract the most accurate chip power model to understand the power behavior of chips in a full-system context. If you don’t yet have the chip layout model at the prototyping stage, create an estimated CPM (chip power model) using Ansys Redhawk tools to anticipate the physics at the initial level. Thermal and power analysis shouldn’t be a signoff step, but an ongoing process because making last-minute changes in the design might not work. Figure3: Power Integrity Analysis using Ansys Redhawk-SC Electrothermal Thermal Integrity: It is extremely important to understand the thermal distribution in the interposer design to regulate thermal integrity. Just power and signal integrity might not save your design from thermal runaway or local thermal failure. with multiple chips close together in a 2.5D package the hotter chiplet might heat up the nearby chiplets and change their power profile, possibly leading to yet more heating. Heat is dissipated from the chips to the interposer and further through TSVs to the substrate, which heats up the entire package. To avoid stress and warpage due to the differential thermal expansion, designers should understand the thermal profile of every chip and interposer in the design. These maps will give insight into the thermal distribution across the IC package, allowing the designer to determine thermal coupling among chips through the interposer. Power dissipation is, of course, driven by activity. Ansys PowerArtist is an RTL power analysis tool that is integrated with in RedHawk-SC Electrothermal to generate the most accurate chip thermal models (CTMs) based on ultra-long, realistic activity vectors produced by hardware emulators. By assembling the entire 3D-IC system including chip CTM, interposer, package, and heat sink, Ansys RedHawk-SC Electrothermal gives the designer an accurate thermal distribution and an understanding of the thermal coupling between chiplets and the interposer. Monitoring temperature gradients needs to start early in the IC package design. The sooner the better. The complete front-to-back flow with gives a clear insight into the thermal distribution over time for the entire package, making your design more reliable. Figure 4: Different parameter extractions for Silicon Interposer Design Signal Integrity: In the IC package, high-speed signals are transmitted from one die to another through an interposer at very high bit rates. The signals are closely spaced and also relatively long (compared to on-chip routing), which makes them vulnerable to electromagnetic interference (EMI) and coupling (EMC). Even digital designers need to follow high speed design guidelines to maintain signal integrity. The only way to control the EMC/EMI is with fast, high-capacity electromagnetic solvers that extract a coupled electromagnetic model including chiplets, signal routing through the interposer, and system coupling effect. With Ansys RaptorHand HFSS easy to analyze all these elements in a single, large model and meet the desired goal of a clean eye diagram. HFSS and Ansys Q3D can also be used to extract RLC parasitics and provide visualization of the electromagnetic fields and scale up to system level extraction beyond the interposer. Learn more about challenges and solutions for 3D-IC and interposers. Semiconductor Design and Simulation Software | Ansys Ansys RedHawk-SC Electrothermal Datasheet Thermal Integrity Challenges and Solutions of Silicon Interposer Design | Ansys ALSO READ: HFSS Leads the Way with Exponential Innovation DesignCon 2023 Panel Photonics future: the vision, the challenge, and the path to infinity & beyond! Exponential Innovation: HFSS Share this post via: * * * * -------------------------------------------------------------------------------- CategoriesAnsys, Inc., Chiplet, EDA Tags2.5d packaging, Ansys PowerArtist, Ansys Redhawk-SC, autonomous vehicle, chiplet, microbump, RaptorHand HFSS, RedHawk-SC Electrothermal COMMENTS There are no comments yet. You must register or log in to view/post comments. POST NAVIGATION Previous PostPrevious Samtec Lights Up MemCon Next PostNext Lithography Resolution Limits: The Point Spread Function SPONSOR ANSYS Company Wiki Executive Interview Podcast EP68: The Foundation of Computational Electromagnetics Most Viewed Blog 2023 Most Viewed Blog 2022 Most Viewed Blog 2021 Most Viewed Blog 2020 Most Viewed Blog 2019 Most Viewed Blog 2018 Most Viewed Blog 2017 Most Viewed Blog 2016 Most Viewed Blog 2015 Most Viewed Blog 2014 Most Viewed Blog 2013 Most Viewed Blog 2012 Most Viewed Blog 2011 GOOGLE TRANSLATE Arabic Chinese (Simplified) Dutch English French German Italian Portuguese Russian Spanish English Instance Array ( [node_name] => Ansys, Inc. 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[_whenSaveable:protected] => Array ( ) [_cascadeSave:protected] => Array ( ) [_behaviors:protected] => ) ) [populated:protected] => 1 ) RECENT ANSYS, INC. PRESS 1. ANSYS NAMES RACHEL PYLES AS CHIEF FINANCIAL OFFICER started by AmandaK on February 21, 2024 2. ANSYS, SCHAEFFLER COLLABORATION DRIVES SUSTAINABLE PRODUCT DEVELOPMENT started by AmandaK on February 21, 2024 3. NEW ANSYS FLUENT WEB UI SUPPORTS ACCESS TO MASSIVE, MULTI-GPU CFD SIMULATIONS started by AmandaK on February 9, 2024 4. ANSYS 2024 R1 REIMAGINES THE USER EXPERIENCE WHILE EXPANDING MULTIPHYSICS SUPERIORITY BOOSTED BY AI started by AmandaK on February 9, 2024 5. ANSYS AND DXOMARK PARTNER ON BREAKTHROUGH SOLUTION TO VALIDATE VIRTUAL CAMERA SYSTEMS started by AmandaK on January 30, 2024 6. ANSYS ANNOUNCES DEEPER COLLABORATION WITH HUMANETICS TO ENHANCE HUMAN SAFETY started by AmandaK on January 30, 2024 7. SYNOPSYS TO ACQUIRE ANSYS, CREATING A LEADER IN SILICON TO SYSTEMS DESIGN SOLUTIONS started by AmandaK on January 17, 2024 8. ANSYS LAUNCHES ANSYS SIMAI™ started by AmandaK on January 16, 2024 9. ANSYS ACCELERATES AUTONOMOUS VEHICLE DEVELOPMENT WITH NVIDIA OMNIVERSE started by AmandaK on January 16, 2024 10. ASTROBOTIC USES ANSYS TO PREPARE FOR HISTORIC LUNAR MISSION started by AmandaK on January 16, 2024 SPONSOR ANSYS Company Wiki Executive Interview Podcast EP68: The Foundation of Computational Electromagnetics Most Viewed Blog 2023 Most Viewed Blog 2022 Most Viewed Blog 2021 Most Viewed Blog 2020 Most Viewed Blog 2019 Most Viewed Blog 2018 Most Viewed Blog 2017 Most Viewed Blog 2016 Most Viewed Blog 2015 Most Viewed Blog 2014 Most Viewed Blog 2013 Most Viewed Blog 2012 Most Viewed Blog 2011 Instance Array ( [node_name] => Ansys, Inc. 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[description] => [node_name] => [node_type_id] => Forum [parent_node_id] => 355 [display_order] => 50 [display_in_list] => 1 [lft] => 37 [rgt] => 38 [depth] => 2 [style_id] => 0 [effective_style_id] => 4 [breadcrumb_data] => {"385":{"node_id":385,"title":"Companies","depth":0,"lft":13,"node_name":null,"node_type_id":"LinkForum","display_in_list":true},"355":{"node_id":355,"title":"Company Forums","depth":1,"lft":14,"node_name":null,"node_type_id":"Category","display_in_list":true}} [navigation_id] => [effective_navigation_id] => ) [_relations:protected] => Array ( ) [_previousValues:protected] => Array ( ) [_options:protected] => Array ( ) [_deleted:protected] => [_readOnly:protected] => [_writePending:protected] => [_writeRunning:protected] => [_errors:protected] => Array ( ) [_whenSaveable:protected] => Array ( ) [_cascadeSave:protected] => Array ( ) [_behaviors:protected] => ) ) [_previousValues:protected] => Array ( ) [_options:protected] => Array ( ) [_deleted:protected] => [_readOnly:protected] => [_writePending:protected] => [_writeRunning:protected] => [_errors:protected] => Array ( ) [_whenSaveable:protected] => Array ( ) [_cascadeSave:protected] => Array ( ) [_behaviors:protected] => ) ) [_previousValues:protected] => Array ( ) [_options:protected] => Array ( ) [_deleted:protected] => [_readOnly:protected] => [_writePending:protected] => [_writeRunning:protected] => [_errors:protected] => Array ( ) [_whenSaveable:protected] => Array ( ) [_cascadeSave:protected] => Array ( ) [_behaviors:protected] => ) ) [populated:protected] => 1 ) RECENT ANSYS, INC. PRESS 1. ANSYS NAMES RACHEL PYLES AS CHIEF FINANCIAL OFFICER started by AmandaK on February 21, 2024 2. ANSYS, SCHAEFFLER COLLABORATION DRIVES SUSTAINABLE PRODUCT DEVELOPMENT started by AmandaK on February 21, 2024 3. NEW ANSYS FLUENT WEB UI SUPPORTS ACCESS TO MASSIVE, MULTI-GPU CFD SIMULATIONS started by AmandaK on February 9, 2024 4. ANSYS 2024 R1 REIMAGINES THE USER EXPERIENCE WHILE EXPANDING MULTIPHYSICS SUPERIORITY BOOSTED BY AI started by AmandaK on February 9, 2024 5. ANSYS AND DXOMARK PARTNER ON BREAKTHROUGH SOLUTION TO VALIDATE VIRTUAL CAMERA SYSTEMS started by AmandaK on January 30, 2024 6. ANSYS ANNOUNCES DEEPER COLLABORATION WITH HUMANETICS TO ENHANCE HUMAN SAFETY started by AmandaK on January 30, 2024 7. SYNOPSYS TO ACQUIRE ANSYS, CREATING A LEADER IN SILICON TO SYSTEMS DESIGN SOLUTIONS started by AmandaK on January 17, 2024 8. ANSYS LAUNCHES ANSYS SIMAI™ started by AmandaK on January 16, 2024 9. ANSYS ACCELERATES AUTONOMOUS VEHICLE DEVELOPMENT WITH NVIDIA OMNIVERSE started by AmandaK on January 16, 2024 10. ASTROBOTIC USES ANSYS TO PREPARE FOR HISTORIC LUNAR MISSION started by AmandaK on January 16, 2024 Blogs JobsWikis Forum All Search Copyright © 2024 SemiWiki.com. All rights reserved. Legal / Sponsor Disclosure - About SemiWiki Originaltext Diese Übersetzung bewerten Mit deinem Feedback können wir Google Übersetzer weiter verbessern