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Access this Webinar now

As semiconductor manufacturing technology continues to advance, the size and
complexity of integrated-circuit designs grow exponentially. Consequently, the
time-to-design-closure of an IC design project becomes not only prolonged but
also uncertain. The impact is especially pressing at digital place & route stage
of the design process.

One major factor causing this tremendous difficulty in design closure at
advanced nodes is the increasing dominance of resistivity to the signal timing.
Capacitance (wire-length) estimation alone is no longer sufficient for precise
and correlated timing analysis at early stage of P&R. A paradigm shift to
detail-route-centric place and route technology, where detail-route wire/via
resistance and signal routing patterns are readily visible to various P&R
stages, is needed to alleviate the challenge to design closure.

In this webinar, we will give an overview of Aprisa Detail-Route-Centric Place &
Route architecture, a technology recently acquired by Siemens EDA for physical
implementation at advanced process nodes. With this technology, timing/power/DRC
and other design metrics are consistent throughout the P&R flow, which reduces
iterations within the flow and helps to achieve fast time-to-design-closure for
your design project.




WHAT YOU WILL LEARN:

 * Introduction to Aprisa Place & Route tool

 * Challenges designers face with advanced technology nodes doing P&R

 * Detail-route-centric architecture to help achieve pre-route to post-route
   correlation

 * Sibling route technology to achieve better timing on high performance cores

 * PowerFirst Technology to optimize best possible power

 * How to achieve fast time to design closure for your design




WHO SHOULD ATTEND:

 * PD/Backend Engineers & Managers

 * CAD Engineers & Managers

 * Design Engineers & Managers




RELATED RESOURCES

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REDUCING IC DESIGN EFFORT WITH EASY-TO-USE RELIABLE DIGITAL IC DESIGN FLOW

IROC Technologies faced developing an integrated circuit (IC) - from scratch -
with limited internal IC design resources. To meet the aggressive tapeout
schedule, IROC needed to feel confident in the new design flow and software.

Article


AIM FOR POWER FIRST FOR BEST PLACE-AND-ROUTE RESULTS

Place-and-route tools employ a variety of strategies to achieve the lowest power
without sacrificing performance

White Paper


APRISA PLACE-AND-ROUTE TOOL FOR LOW-POWER SOCS

A digital place-and-route methodology for lowest-power-optimized PPA






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